(untitled) (Моделювання, керування та інформаційні технології, 2025)
In order to expand the functionality by increasing the number and complexity of nonlinear multi-input functions and transformations performed, in this paper we consider the urgent need for creating high-performance hardware image processors (IP). Such IPs are designed based on a conceptual approach, the essence of which is to rank the processed signals (pixels), fast command-controlled selection of rank differences with their subsequent weight addition. And since these procedures are basic for all advanced models of convolutional neural networks (CNNs), such IP can play the role of not only high-speed pre-filtering devices, but also be self-learning reconfigurable accelerators for CNNs, associative memory models, clustering and pattern recognition. First, we briefly review related works in order to show the advantages of using the proposed concept and equivalence models (EMs). The capacity and recognition properties of NNs based on modified EMs exceed the similar indicators of traditional networks by orders of magnitude. Therefore, such EM-neuroparadigm is promising for processing, recognition of large-sized images, including highly correlated, high-noise images. And since the main nodes of EMs are filtering nodes and procedures with continuous-logical operations, in this article we consider approaches to the design of IPs with extended functionality. The proposed structure of the processor based on our concept and the FPGA Altera EP3C16F484 Cyclone III family chip. The design results and calculations show that it is possible to implement IP for an image size of 64*64 and a window of 3*3 in a single crystal. For 2.5 V and a clock frequency of 200MHz, the power consumption will be at the level of 200mW, and the time for calculating the filter pixels will be 25ns. The results confirm the correctness of the concept.